<HTML><HEAD><TITLE>Device Usage Statistics Report</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'><H3>Device Usage Page (usage_statistics_webtalk.html)</H3>This HTML page displays the device usage statistics that will be sent to Xilinx.<BR>To see the actual file transmitted to Xilinx, please click <A HREF="./usage_statistics_webtalk.xml">here</A>.<BR><BR><HR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>software_version_and_target_device</B></TD></TR>
<TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>beta</B></TD><TD>FALSE</TD>
  <TD BGCOLOR='#DBE5F1'><B>build_version</B></TD><TD>2552052</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>date_generated</B></TD><TD>Sat Nov 11 14:25:44 2023</TD>
  <TD BGCOLOR='#DBE5F1'><B>os_platform</B></TD><TD>WIN64</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>product_version</B></TD><TD>Vivado v2019.1 (64-bit)</TD>
  <TD BGCOLOR='#DBE5F1'><B>project_id</B></TD><TD>9a488ef657fc45f3a012b0a9077568fd</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>project_iteration</B></TD><TD>47</TD>
  <TD BGCOLOR='#DBE5F1'><B>random_id</B></TD><TD>a4f83330c7005dcbb4157ff78318ed28</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>registration_id</B></TD><TD>a4f83330c7005dcbb4157ff78318ed28</TD>
  <TD BGCOLOR='#DBE5F1'><B>route_design</B></TD><TD>TRUE</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>target_device</B></TD><TD>xc7z010</TD>
  <TD BGCOLOR='#DBE5F1'><B>target_family</B></TD><TD>zynq</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>target_package</B></TD><TD>clg400</TD>
  <TD BGCOLOR='#DBE5F1'><B>target_speed</B></TD><TD>-2</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>tool_flow</B></TD><TD>Vivado</TD>
</TR> </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>user_environment</B></TD></TR>
<TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>cpu_name</B></TD><TD>12th Gen Intel(R) Core(TM) i7-12700H</TD>
  <TD BGCOLOR='#DBE5F1'><B>cpu_speed</B></TD><TD>2688 MHz</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>os_name</B></TD><TD>Windows Server 2016 or Windows 10</TD>
  <TD BGCOLOR='#DBE5F1'><B>os_release</B></TD><TD>major release  (build 9200)</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>system_ram</B></TD><TD>16.000 GB</TD>
  <TD BGCOLOR='#DBE5F1'><B>total_processors</B></TD><TD>1</TD>
</TR> </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>vivado_usage</B></TD></TR>
<TR ALIGN='LEFT'>  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>gui_handlers</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>addsrcwizard_specify_simulation_specific_hdl_files=1</TD>
   <TD>basedialog_apply=1</TD>
   <TD>basedialog_cancel=6</TD>
   <TD>basedialog_ok=135</TD>
</TR><TR ALIGN='LEFT'>   <TD>basedialog_yes=44</TD>
   <TD>cmdmsgdialog_copy_message=2</TD>
   <TD>cmdmsgdialog_messages=3</TD>
   <TD>cmdmsgdialog_ok=4</TD>
</TR><TR ALIGN='LEFT'>   <TD>coretreetablepanel_core_tree_table=6</TD>
   <TD>createconstraintsfilepanel_file_name=1</TD>
   <TD>createsrcfiledialog_file_name=13</TD>
   <TD>definemodulesdialog_new_source_files=5</TD>
</TR><TR ALIGN='LEFT'>   <TD>filesetpanel_file_set_panel_tree=49</TD>
   <TD>flownavigatortreepanel_flow_navigator_tree=109</TD>
   <TD>fpgachooser_fpga_table=1</TD>
   <TD>graphicalview_zoom_fit=5</TD>
</TR><TR ALIGN='LEFT'>   <TD>hardwaretreepanel_hardware_tree_table=58</TD>
   <TD>mainmenumgr_checkpoint=4</TD>
   <TD>mainmenumgr_edit=6</TD>
   <TD>mainmenumgr_file=18</TD>
</TR><TR ALIGN='LEFT'>   <TD>mainmenumgr_ip=3</TD>
   <TD>mainmenumgr_open_recent_project=4</TD>
   <TD>mainmenumgr_project=9</TD>
   <TD>mainmenumgr_simulation_waveform=3</TD>
</TR><TR ALIGN='LEFT'>   <TD>mainmenumgr_text_editor=1</TD>
   <TD>mainwintoolbarmgr_select_or_save_window_layout=1</TD>
   <TD>msgtreepanel_message_view_tree=1</TD>
   <TD>pacommandnames_add_sources=5</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_auto_connect_target=9</TD>
   <TD>pacommandnames_auto_update_hier=7</TD>
   <TD>pacommandnames_new_project=2</TD>
   <TD>pacommandnames_program_fpga=47</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_reports_window=5</TD>
   <TD>pacommandnames_run_bitgen=2</TD>
   <TD>pacommandnames_run_implementation=1</TD>
   <TD>pacommandnames_set_as_top=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_simulation_live_break=6</TD>
   <TD>pacommandnames_simulation_live_run_all=6</TD>
   <TD>pacommandnames_simulation_relaunch=6</TD>
   <TD>pacommandnames_simulation_run_behavioral=32</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_simulation_run_post_synthesis_functional=1</TD>
   <TD>paviews_code=1</TD>
   <TD>paviews_device=1</TD>
   <TD>paviews_package=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>paviews_project_summary=11</TD>
   <TD>programfpgadialog_program=47</TD>
   <TD>progressdialog_cancel=2</TD>
   <TD>projectnamechooser_choose_project_location=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>projectnamechooser_project_name=1</TD>
   <TD>projectsettingssimulationpanel_target_simulator=1</TD>
   <TD>projecttab_close_design=1</TD>
   <TD>projecttab_reload=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>rdicommands_copy=1</TD>
   <TD>rdicommands_delete=2</TD>
   <TD>rdicommands_settings=2</TD>
   <TD>rdiviews_waveform_viewer=19</TD>
</TR><TR ALIGN='LEFT'>   <TD>rungadget_show_warning_and_error_messages_in_messages=1</TD>
   <TD>saveprojectutils_dont_save=2</TD>
   <TD>settingsdialog_project_tree=1</TD>
   <TD>signaltreepanel_signal_tree_table=10</TD>
</TR><TR ALIGN='LEFT'>   <TD>simpleoutputproductdialog_generate_output_products_immediately=3</TD>
   <TD>simulationscopespanel_simulate_scope_table=13</TD>
   <TD>srcchooserpanel_create_file=10</TD>
   <TD>srcmenu_ip_hierarchy=3</TD>
</TR><TR ALIGN='LEFT'>   <TD>stalerundialog_open_design=1</TD>
   <TD>syntheticagettingstartedview_recent_projects=5</TD>
   <TD>waveformnametree_waveform_name_tree=18</TD>
</TR>  </TABLE>
  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>java_command_handlers</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>addsources=5</TD>
   <TD>autoconnecttarget=9</TD>
   <TD>coreview=2</TD>
   <TD>customizecore=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>editdelete=2</TD>
   <TD>launchprogramfpga=47</TD>
   <TD>newproject=2</TD>
   <TD>openhardwaremanager=7</TD>
</TR><TR ALIGN='LEFT'>   <TD>recustomizecore=4</TD>
   <TD>runbitgen=48</TD>
   <TD>runimplementation=2</TD>
   <TD>runsynthesis=9</TD>
</TR><TR ALIGN='LEFT'>   <TD>savedesign=1</TD>
   <TD>settopnode=1</TD>
   <TD>showview=49</TD>
   <TD>simulationbreak=6</TD>
</TR><TR ALIGN='LEFT'>   <TD>simulationrelaunch=6</TD>
   <TD>simulationrun=33</TD>
   <TD>simulationrunall=6</TD>
   <TD>toolssettings=3</TD>
</TR><TR ALIGN='LEFT'>   <TD>viewlayoutcmd=1</TD>
   <TD>viewtaskprojectmanager=5</TD>
   <TD>viewtasksynthesis=3</TD>
</TR>  </TABLE>
</TR><TR ALIGN='LEFT'>  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>other_data</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>guimode=16</TD>
</TR>  </TABLE>
  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>project_data</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>constraintsetcount=1</TD>
   <TD>core_container=false</TD>
   <TD>currentimplrun=impl_1</TD>
   <TD>currentsynthesisrun=synth_1</TD>
</TR><TR ALIGN='LEFT'>   <TD>default_library=xil_defaultlib</TD>
   <TD>designmode=RTL</TD>
   <TD>export_simulation_activehdl=3</TD>
   <TD>export_simulation_ies=3</TD>
</TR><TR ALIGN='LEFT'>   <TD>export_simulation_modelsim=3</TD>
   <TD>export_simulation_questa=3</TD>
   <TD>export_simulation_riviera=3</TD>
   <TD>export_simulation_vcs=3</TD>
</TR><TR ALIGN='LEFT'>   <TD>export_simulation_xsim=3</TD>
   <TD>implstrategy=Vivado Implementation Defaults</TD>
   <TD>launch_simulation_activehdl=0</TD>
   <TD>launch_simulation_ies=0</TD>
</TR><TR ALIGN='LEFT'>   <TD>launch_simulation_modelsim=32</TD>
   <TD>launch_simulation_questa=0</TD>
   <TD>launch_simulation_riviera=0</TD>
   <TD>launch_simulation_vcs=0</TD>
</TR><TR ALIGN='LEFT'>   <TD>launch_simulation_xsim=13</TD>
   <TD>simulator_language=Mixed</TD>
   <TD>srcsetcount=7</TD>
   <TD>synthesisstrategy=Vivado Synthesis Defaults</TD>
</TR><TR ALIGN='LEFT'>   <TD>target_language=Verilog</TD>
   <TD>target_simulator=ModelSim</TD>
   <TD>totalimplruns=3</TD>
   <TD>totalsynthesisruns=3</TD>
</TR>  </TABLE>
</TR> </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>unisim_transformation</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>post_unisim_transformation</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bufg=4</TD>
    <TD>carry4=32</TD>
    <TD>fdce=112</TD>
    <TD>fdpe=6</TD>
</TR><TR ALIGN='LEFT'>    <TD>fdre=74</TD>
    <TD>fdse=4</TD>
    <TD>gnd=23</TD>
    <TD>ibuf=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut1=10</TD>
    <TD>lut2=44</TD>
    <TD>lut3=10</TD>
    <TD>lut4=45</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut5=43</TD>
    <TD>lut6=26</TD>
    <TD>mmcme2_adv=1</TD>
    <TD>obuf=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb18e1=1</TD>
    <TD>vcc=16</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>pre_unisim_transformation</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bufg=4</TD>
    <TD>carry4=32</TD>
    <TD>fdce=112</TD>
    <TD>fdpe=6</TD>
</TR><TR ALIGN='LEFT'>    <TD>fdre=74</TD>
    <TD>fdse=4</TD>
    <TD>gnd=23</TD>
    <TD>ibuf=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut1=10</TD>
    <TD>lut2=44</TD>
    <TD>lut3=10</TD>
    <TD>lut4=45</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut5=43</TD>
    <TD>lut6=26</TD>
    <TD>mmcme2_adv=1</TD>
    <TD>obuf=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb18e1=1</TD>
    <TD>vcc=16</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>power_opt_design</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options_spo</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-cell_types=default::all</TD>
    <TD>-clocks=default::[not_specified]</TD>
    <TD>-exclude_cells=default::[not_specified]</TD>
    <TD>-include_cells=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bram_ports_augmented=0</TD>
    <TD>bram_ports_newly_gated=0</TD>
    <TD>bram_ports_total=2</TD>
    <TD>flow_state=default</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_registers_augmented=0</TD>
    <TD>slice_registers_newly_gated=0</TD>
    <TD>slice_registers_total=196</TD>
    <TD>srls_augmented=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>srls_newly_gated=0</TD>
    <TD>srls_total=0</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>ip_statistics</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>clk_wiz_v6_0_3_0_0/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>clkin1_period=20.000</TD>
    <TD>clkin2_period=10.0</TD>
    <TD>clock_mgr_type=NA</TD>
    <TD>component_name=clk_pll_50</TD>
</TR><TR ALIGN='LEFT'>    <TD>core_container=NA</TD>
    <TD>enable_axi=0</TD>
    <TD>feedback_source=FDBK_AUTO</TD>
    <TD>feedback_type=SINGLE</TD>
</TR><TR ALIGN='LEFT'>    <TD>iptotal=1</TD>
    <TD>manual_override=false</TD>
    <TD>num_out_clk=1</TD>
    <TD>primitive=MMCM</TD>
</TR><TR ALIGN='LEFT'>    <TD>use_dyn_phase_shift=false</TD>
    <TD>use_dyn_reconfig=false</TD>
    <TD>use_inclk_stopped=false</TD>
    <TD>use_inclk_switchover=false</TD>
</TR><TR ALIGN='LEFT'>    <TD>use_locked=true</TD>
    <TD>use_max_i_jitter=false</TD>
    <TD>use_min_o_jitter=false</TD>
    <TD>use_phase_alignment=true</TD>
</TR><TR ALIGN='LEFT'>    <TD>use_power_down=false</TD>
    <TD>use_reset=false</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>fifo_generator_v13_2_4/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>c_add_ngc_constraint=0</TD>
    <TD>c_application_type_axis=0</TD>
    <TD>c_application_type_rach=0</TD>
    <TD>c_application_type_rdch=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_application_type_wach=0</TD>
    <TD>c_application_type_wdch=0</TD>
    <TD>c_application_type_wrch=0</TD>
    <TD>c_axi_addr_width=32</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_axi_aruser_width=1</TD>
    <TD>c_axi_awuser_width=1</TD>
    <TD>c_axi_buser_width=1</TD>
    <TD>c_axi_data_width=64</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_axi_id_width=1</TD>
    <TD>c_axi_len_width=8</TD>
    <TD>c_axi_lock_width=1</TD>
    <TD>c_axi_ruser_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_axi_type=1</TD>
    <TD>c_axi_wuser_width=1</TD>
    <TD>c_axis_tdata_width=8</TD>
    <TD>c_axis_tdest_width=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_axis_tid_width=1</TD>
    <TD>c_axis_tkeep_width=1</TD>
    <TD>c_axis_tstrb_width=1</TD>
    <TD>c_axis_tuser_width=4</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_axis_type=0</TD>
    <TD>c_common_clock=1</TD>
    <TD>c_count_type=0</TD>
    <TD>c_data_count_width=10</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_default_value=BlankString</TD>
    <TD>c_din_width=8</TD>
    <TD>c_din_width_axis=1</TD>
    <TD>c_din_width_rach=32</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_din_width_rdch=64</TD>
    <TD>c_din_width_wach=1</TD>
    <TD>c_din_width_wdch=64</TD>
    <TD>c_din_width_wrch=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_dout_rst_val=0</TD>
    <TD>c_dout_width=8</TD>
    <TD>c_en_safety_ckt=0</TD>
    <TD>c_enable_rlocs=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_enable_rst_sync=1</TD>
    <TD>c_error_injection_type=0</TD>
    <TD>c_error_injection_type_axis=0</TD>
    <TD>c_error_injection_type_rach=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_error_injection_type_rdch=0</TD>
    <TD>c_error_injection_type_wach=0</TD>
    <TD>c_error_injection_type_wdch=0</TD>
    <TD>c_error_injection_type_wrch=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_family=zynq</TD>
    <TD>c_full_flags_rst_val=0</TD>
    <TD>c_has_almost_empty=0</TD>
    <TD>c_has_almost_full=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_axi_aruser=0</TD>
    <TD>c_has_axi_awuser=0</TD>
    <TD>c_has_axi_buser=0</TD>
    <TD>c_has_axi_id=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_axi_rd_channel=1</TD>
    <TD>c_has_axi_ruser=0</TD>
    <TD>c_has_axi_wr_channel=1</TD>
    <TD>c_has_axi_wuser=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_axis_tdata=1</TD>
    <TD>c_has_axis_tdest=0</TD>
    <TD>c_has_axis_tid=0</TD>
    <TD>c_has_axis_tkeep=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_axis_tlast=0</TD>
    <TD>c_has_axis_tready=1</TD>
    <TD>c_has_axis_tstrb=0</TD>
    <TD>c_has_axis_tuser=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_backup=0</TD>
    <TD>c_has_data_count=0</TD>
    <TD>c_has_data_counts_axis=0</TD>
    <TD>c_has_data_counts_rach=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_data_counts_rdch=0</TD>
    <TD>c_has_data_counts_wach=0</TD>
    <TD>c_has_data_counts_wdch=0</TD>
    <TD>c_has_data_counts_wrch=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_int_clk=0</TD>
    <TD>c_has_master_ce=0</TD>
    <TD>c_has_meminit_file=0</TD>
    <TD>c_has_overflow=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_prog_flags_axis=0</TD>
    <TD>c_has_prog_flags_rach=0</TD>
    <TD>c_has_prog_flags_rdch=0</TD>
    <TD>c_has_prog_flags_wach=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_prog_flags_wdch=0</TD>
    <TD>c_has_prog_flags_wrch=0</TD>
    <TD>c_has_rd_data_count=0</TD>
    <TD>c_has_rd_rst=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_rst=0</TD>
    <TD>c_has_slave_ce=0</TD>
    <TD>c_has_srst=1</TD>
    <TD>c_has_underflow=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_has_valid=0</TD>
    <TD>c_has_wr_ack=0</TD>
    <TD>c_has_wr_data_count=0</TD>
    <TD>c_has_wr_rst=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_implementation_type=0</TD>
    <TD>c_implementation_type_axis=1</TD>
    <TD>c_implementation_type_rach=1</TD>
    <TD>c_implementation_type_rdch=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_implementation_type_wach=1</TD>
    <TD>c_implementation_type_wdch=1</TD>
    <TD>c_implementation_type_wrch=1</TD>
    <TD>c_init_wr_pntr_val=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_interface_type=0</TD>
    <TD>c_memory_type=1</TD>
    <TD>c_mif_file_name=BlankString</TD>
    <TD>c_msgon_val=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_optimization_mode=0</TD>
    <TD>c_overflow_low=0</TD>
    <TD>c_power_saving_mode=0</TD>
    <TD>c_preload_latency=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_preload_regs=0</TD>
    <TD>c_prim_fifo_type=1kx18</TD>
    <TD>c_prim_fifo_type_axis=1kx18</TD>
    <TD>c_prim_fifo_type_rach=512x36</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_prim_fifo_type_rdch=1kx36</TD>
    <TD>c_prim_fifo_type_wach=512x36</TD>
    <TD>c_prim_fifo_type_wdch=1kx36</TD>
    <TD>c_prim_fifo_type_wrch=512x36</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_prog_empty_thresh_assert_val=2</TD>
    <TD>c_prog_empty_thresh_assert_val_axis=1022</TD>
    <TD>c_prog_empty_thresh_assert_val_rach=1022</TD>
    <TD>c_prog_empty_thresh_assert_val_rdch=1022</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_prog_empty_thresh_assert_val_wach=1022</TD>
    <TD>c_prog_empty_thresh_assert_val_wdch=1022</TD>
    <TD>c_prog_empty_thresh_assert_val_wrch=1022</TD>
    <TD>c_prog_empty_thresh_negate_val=3</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_prog_empty_type=0</TD>
    <TD>c_prog_empty_type_axis=0</TD>
    <TD>c_prog_empty_type_rach=0</TD>
    <TD>c_prog_empty_type_rdch=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_prog_empty_type_wach=0</TD>
    <TD>c_prog_empty_type_wdch=0</TD>
    <TD>c_prog_empty_type_wrch=0</TD>
    <TD>c_prog_full_thresh_assert_val=1022</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_prog_full_thresh_assert_val_axis=1023</TD>
    <TD>c_prog_full_thresh_assert_val_rach=1023</TD>
    <TD>c_prog_full_thresh_assert_val_rdch=1023</TD>
    <TD>c_prog_full_thresh_assert_val_wach=1023</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_prog_full_thresh_assert_val_wdch=1023</TD>
    <TD>c_prog_full_thresh_assert_val_wrch=1023</TD>
    <TD>c_prog_full_thresh_negate_val=1021</TD>
    <TD>c_prog_full_type=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_prog_full_type_axis=0</TD>
    <TD>c_prog_full_type_rach=0</TD>
    <TD>c_prog_full_type_rdch=0</TD>
    <TD>c_prog_full_type_wach=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_prog_full_type_wdch=0</TD>
    <TD>c_prog_full_type_wrch=0</TD>
    <TD>c_rach_type=0</TD>
    <TD>c_rd_data_count_width=10</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_rd_depth=1024</TD>
    <TD>c_rd_freq=1</TD>
    <TD>c_rd_pntr_width=10</TD>
    <TD>c_rdch_type=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_reg_slice_mode_axis=0</TD>
    <TD>c_reg_slice_mode_rach=0</TD>
    <TD>c_reg_slice_mode_rdch=0</TD>
    <TD>c_reg_slice_mode_wach=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_reg_slice_mode_wdch=0</TD>
    <TD>c_reg_slice_mode_wrch=0</TD>
    <TD>c_select_xpm=0</TD>
    <TD>c_synchronizer_stage=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_underflow_low=0</TD>
    <TD>c_use_common_overflow=0</TD>
    <TD>c_use_common_underflow=0</TD>
    <TD>c_use_default_settings=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_use_dout_rst=1</TD>
    <TD>c_use_ecc=0</TD>
    <TD>c_use_ecc_axis=0</TD>
    <TD>c_use_ecc_rach=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_use_ecc_rdch=0</TD>
    <TD>c_use_ecc_wach=0</TD>
    <TD>c_use_ecc_wdch=0</TD>
    <TD>c_use_ecc_wrch=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_use_embedded_reg=0</TD>
    <TD>c_use_fifo16_flags=0</TD>
    <TD>c_use_fwft_data_count=0</TD>
    <TD>c_use_pipeline_reg=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_valid_low=0</TD>
    <TD>c_wach_type=0</TD>
    <TD>c_wdch_type=0</TD>
    <TD>c_wr_ack_low=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_wr_data_count_width=10</TD>
    <TD>c_wr_depth=1024</TD>
    <TD>c_wr_depth_axis=1024</TD>
    <TD>c_wr_depth_rach=16</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_wr_depth_rdch=1024</TD>
    <TD>c_wr_depth_wach=16</TD>
    <TD>c_wr_depth_wdch=1024</TD>
    <TD>c_wr_depth_wrch=16</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_wr_freq=1</TD>
    <TD>c_wr_pntr_width=10</TD>
    <TD>c_wr_pntr_width_axis=10</TD>
    <TD>c_wr_pntr_width_rach=4</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_wr_pntr_width_rdch=10</TD>
    <TD>c_wr_pntr_width_wach=4</TD>
    <TD>c_wr_pntr_width_wdch=10</TD>
    <TD>c_wr_pntr_width_wrch=4</TD>
</TR><TR ALIGN='LEFT'>    <TD>c_wr_response_latency=1</TD>
    <TD>c_wrch_type=0</TD>
    <TD>core_container=false</TD>
    <TD>iptotal=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipcorerevision=4</TD>
    <TD>x_iplanguage=VERILOG</TD>
    <TD>x_iplibrary=ip</TD>
    <TD>x_ipname=fifo_generator</TD>
</TR><TR ALIGN='LEFT'>    <TD>x_ipproduct=Vivado 2019.1</TD>
    <TD>x_ipsimlanguage=MIXED</TD>
    <TD>x_ipvendor=xilinx.com</TD>
    <TD>x_ipversion=13.2</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_drc</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-append=default::[not_specified]</TD>
    <TD>-checks=default::[not_specified]</TD>
    <TD>-fail_on=default::[not_specified]</TD>
    <TD>-force=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-format=default::[not_specified]</TD>
    <TD>-internal=default::[not_specified]</TD>
    <TD>-internal_only=default::[not_specified]</TD>
    <TD>-messages=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-name=default::[not_specified]</TD>
    <TD>-no_waivers=default::[not_specified]</TD>
    <TD>-return_string=default::[not_specified]</TD>
    <TD>-ruledecks=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-upgrade_cw=default::[not_specified]</TD>
    <TD>-waived=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>results</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>reqp-1840=4</TD>
    <TD>rtstat-10=1</TD>
    <TD>zps7-1=1</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_methodology</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-append=default::[not_specified]</TD>
    <TD>-checks=default::[not_specified]</TD>
    <TD>-fail_on=default::[not_specified]</TD>
    <TD>-force=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-format=default::[not_specified]</TD>
    <TD>-messages=default::[not_specified]</TD>
    <TD>-name=default::[not_specified]</TD>
    <TD>-return_string=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-slack_lesser_than=default::[not_specified]</TD>
    <TD>-waived=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>results</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>lutar-1=1</TD>
    <TD>timing-17=155</TD>
    <TD>timing-18=1</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_power</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-advisory=default::[not_specified]</TD>
    <TD>-append=default::[not_specified]</TD>
    <TD>-file=[specified]</TD>
    <TD>-format=default::text</TD>
</TR><TR ALIGN='LEFT'>    <TD>-hier=default::power</TD>
    <TD>-hierarchical_depth=default::4</TD>
    <TD>-l=default::[not_specified]</TD>
    <TD>-name=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-no_propagation=default::[not_specified]</TD>
    <TD>-return_string=default::[not_specified]</TD>
    <TD>-rpx=[specified]</TD>
    <TD>-verbose=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-vid=default::[not_specified]</TD>
    <TD>-xpe=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>airflow=250 (LFM)</TD>
    <TD>ambient_temp=25.0 (C)</TD>
    <TD>bi-dir_toggle=12.500000</TD>
    <TD>bidir_output_enable=1.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>board_layers=8to11 (8 to 11 Layers)</TD>
    <TD>board_selection=medium (10&quot;x10&quot;)</TD>
    <TD>bram=0.000000</TD>
    <TD>clocks=0.000599</TD>
</TR><TR ALIGN='LEFT'>    <TD>confidence_level_clock_activity=Low</TD>
    <TD>confidence_level_design_state=High</TD>
    <TD>confidence_level_device_models=High</TD>
    <TD>confidence_level_internal_activity=Medium</TD>
</TR><TR ALIGN='LEFT'>    <TD>confidence_level_io_activity=Medium</TD>
    <TD>confidence_level_overall=Low</TD>
    <TD>customer=TBD</TD>
    <TD>customer_class=TBD</TD>
</TR><TR ALIGN='LEFT'>    <TD>devstatic=0.090816</TD>
    <TD>die=xc7z010clg400-2</TD>
    <TD>dsp_output_toggle=12.500000</TD>
    <TD>dynamic=0.106035</TD>
</TR><TR ALIGN='LEFT'>    <TD>effective_thetaja=11.5</TD>
    <TD>enable_probability=0.990000</TD>
    <TD>family=zynq</TD>
    <TD>ff_toggle=12.500000</TD>
</TR><TR ALIGN='LEFT'>    <TD>flow_state=routed</TD>
    <TD>heatsink=none</TD>
    <TD>i/o=0.000034</TD>
    <TD>input_toggle=12.500000</TD>
</TR><TR ALIGN='LEFT'>    <TD>junction_temp=27.3 (C)</TD>
    <TD>logic=0.000116</TD>
    <TD>mgtavcc_dynamic_current=0.000000</TD>
    <TD>mgtavcc_static_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>mgtavcc_total_current=0.000000</TD>
    <TD>mgtavcc_voltage=1.000000</TD>
    <TD>mgtavtt_dynamic_current=0.000000</TD>
    <TD>mgtavtt_static_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>mgtavtt_total_current=0.000000</TD>
    <TD>mgtavtt_voltage=1.200000</TD>
    <TD>mgtvccaux_dynamic_current=0.000000</TD>
    <TD>mgtvccaux_static_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>mgtvccaux_total_current=0.000000</TD>
    <TD>mgtvccaux_voltage=1.800000</TD>
    <TD>mmcm=0.105165</TD>
    <TD>netlist_net_matched=NA</TD>
</TR><TR ALIGN='LEFT'>    <TD>off-chip_power=0.000000</TD>
    <TD>on-chip_power=0.196851</TD>
    <TD>output_enable=1.000000</TD>
    <TD>output_load=5.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>output_toggle=12.500000</TD>
    <TD>package=clg400</TD>
    <TD>pct_clock_constrained=0.000000</TD>
    <TD>pct_inputs_defined=50</TD>
</TR><TR ALIGN='LEFT'>    <TD>platform=nt64</TD>
    <TD>process=typical</TD>
    <TD>ram_enable=50.000000</TD>
    <TD>ram_write=50.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>read_saif=False</TD>
    <TD>set/reset_probability=0.000000</TD>
    <TD>signal_rate=False</TD>
    <TD>signals=0.000121</TD>
</TR><TR ALIGN='LEFT'>    <TD>simulation_file=None</TD>
    <TD>speedgrade=-2</TD>
    <TD>static_prob=False</TD>
    <TD>temp_grade=commercial</TD>
</TR><TR ALIGN='LEFT'>    <TD>thetajb=9.3 (C/W)</TD>
    <TD>thetasa=0.0 (C/W)</TD>
    <TD>toggle_rate=False</TD>
    <TD>user_board_temp=25.0 (C)</TD>
</TR><TR ALIGN='LEFT'>    <TD>user_effective_thetaja=11.5</TD>
    <TD>user_junc_temp=27.3 (C)</TD>
    <TD>user_thetajb=9.3 (C/W)</TD>
    <TD>user_thetasa=0.0 (C/W)</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccadc_dynamic_current=0.000000</TD>
    <TD>vccadc_static_current=0.020000</TD>
    <TD>vccadc_total_current=0.020000</TD>
    <TD>vccadc_voltage=1.800000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccaux_dynamic_current=0.058309</TD>
    <TD>vccaux_io_dynamic_current=0.000000</TD>
    <TD>vccaux_io_static_current=0.000000</TD>
    <TD>vccaux_io_total_current=0.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccaux_io_voltage=1.800000</TD>
    <TD>vccaux_static_current=0.005462</TD>
    <TD>vccaux_total_current=0.063770</TD>
    <TD>vccaux_voltage=1.800000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccbram_dynamic_current=0.000000</TD>
    <TD>vccbram_static_current=0.000240</TD>
    <TD>vccbram_total_current=0.000240</TD>
    <TD>vccbram_voltage=1.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccint_dynamic_current=0.001079</TD>
    <TD>vccint_static_current=0.003852</TD>
    <TD>vccint_total_current=0.004931</TD>
    <TD>vccint_voltage=1.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco12_dynamic_current=0.000000</TD>
    <TD>vcco12_static_current=0.000000</TD>
    <TD>vcco12_total_current=0.000000</TD>
    <TD>vcco12_voltage=1.200000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco135_dynamic_current=0.000000</TD>
    <TD>vcco135_static_current=0.000000</TD>
    <TD>vcco135_total_current=0.000000</TD>
    <TD>vcco135_voltage=1.350000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco15_dynamic_current=0.000000</TD>
    <TD>vcco15_static_current=0.000000</TD>
    <TD>vcco15_total_current=0.000000</TD>
    <TD>vcco15_voltage=1.500000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco18_dynamic_current=0.000000</TD>
    <TD>vcco18_static_current=0.000000</TD>
    <TD>vcco18_total_current=0.000000</TD>
    <TD>vcco18_voltage=1.800000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco25_dynamic_current=0.000000</TD>
    <TD>vcco25_static_current=0.000000</TD>
    <TD>vcco25_total_current=0.000000</TD>
    <TD>vcco25_voltage=2.500000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco33_dynamic_current=0.000000</TD>
    <TD>vcco33_static_current=0.000000</TD>
    <TD>vcco33_total_current=0.000000</TD>
    <TD>vcco33_voltage=3.300000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco_ddr_dynamic_current=0.000000</TD>
    <TD>vcco_ddr_static_current=0.000000</TD>
    <TD>vcco_ddr_total_current=0.000000</TD>
    <TD>vcco_ddr_voltage=1.500000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco_mio0_dynamic_current=0.000000</TD>
    <TD>vcco_mio0_static_current=0.000000</TD>
    <TD>vcco_mio0_total_current=0.000000</TD>
    <TD>vcco_mio0_voltage=1.800000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcco_mio1_dynamic_current=0.000000</TD>
    <TD>vcco_mio1_static_current=0.000000</TD>
    <TD>vcco_mio1_total_current=0.000000</TD>
    <TD>vcco_mio1_voltage=1.800000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccpaux_dynamic_current=0.000000</TD>
    <TD>vccpaux_static_current=0.010330</TD>
    <TD>vccpaux_total_current=0.010330</TD>
    <TD>vccpaux_voltage=1.800000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccpint_dynamic_current=0.000000</TD>
    <TD>vccpint_static_current=0.016899</TD>
    <TD>vccpint_total_current=0.016899</TD>
    <TD>vccpint_voltage=1.000000</TD>
</TR><TR ALIGN='LEFT'>    <TD>vccpll_dynamic_current=0.000000</TD>
    <TD>vccpll_static_current=0.003000</TD>
    <TD>vccpll_total_current=0.003000</TD>
    <TD>vccpll_voltage=1.800000</TD>
</TR><TR ALIGN='LEFT'>    <TD>version=2019.1</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_utilization</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>clocking</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bufgctrl_available=32</TD>
    <TD>bufgctrl_fixed=0</TD>
    <TD>bufgctrl_used=4</TD>
    <TD>bufgctrl_util_percentage=12.50</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufhce_available=48</TD>
    <TD>bufhce_fixed=0</TD>
    <TD>bufhce_used=0</TD>
    <TD>bufhce_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufio_available=8</TD>
    <TD>bufio_fixed=0</TD>
    <TD>bufio_used=0</TD>
    <TD>bufio_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufmrce_available=4</TD>
    <TD>bufmrce_fixed=0</TD>
    <TD>bufmrce_used=0</TD>
    <TD>bufmrce_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufr_available=8</TD>
    <TD>bufr_fixed=0</TD>
    <TD>bufr_used=0</TD>
    <TD>bufr_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>mmcme2_adv_available=2</TD>
    <TD>mmcme2_adv_fixed=0</TD>
    <TD>mmcme2_adv_used=1</TD>
    <TD>mmcme2_adv_util_percentage=50.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>plle2_adv_available=2</TD>
    <TD>plle2_adv_fixed=0</TD>
    <TD>plle2_adv_used=0</TD>
    <TD>plle2_adv_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>dsp</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>dsps_available=80</TD>
    <TD>dsps_fixed=0</TD>
    <TD>dsps_used=0</TD>
    <TD>dsps_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>io_standard</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>blvds_25=0</TD>
    <TD>diff_hstl_i=0</TD>
    <TD>diff_hstl_i_18=0</TD>
    <TD>diff_hstl_ii=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_hstl_ii_18=0</TD>
    <TD>diff_hsul_12=0</TD>
    <TD>diff_mobile_ddr=0</TD>
    <TD>diff_sstl135=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_sstl135_r=0</TD>
    <TD>diff_sstl15=0</TD>
    <TD>diff_sstl15_r=0</TD>
    <TD>diff_sstl18_i=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_sstl18_ii=0</TD>
    <TD>hstl_i=0</TD>
    <TD>hstl_i_18=0</TD>
    <TD>hstl_ii=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>hstl_ii_18=0</TD>
    <TD>hsul_12=0</TD>
    <TD>lvcmos12=0</TD>
    <TD>lvcmos15=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lvcmos18=0</TD>
    <TD>lvcmos25=0</TD>
    <TD>lvcmos33=1</TD>
    <TD>lvds_25=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lvttl=0</TD>
    <TD>mini_lvds_25=0</TD>
    <TD>mobile_ddr=0</TD>
    <TD>pci33_3=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>ppds_25=0</TD>
    <TD>rsds_25=0</TD>
    <TD>sstl135=0</TD>
    <TD>sstl135_r=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>sstl15=0</TD>
    <TD>sstl15_r=0</TD>
    <TD>sstl18_i=0</TD>
    <TD>sstl18_ii=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>tmds_33=0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>memory</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>block_ram_tile_available=60</TD>
    <TD>block_ram_tile_fixed=0</TD>
    <TD>block_ram_tile_used=0.5</TD>
    <TD>block_ram_tile_util_percentage=0.83</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb18_available=120</TD>
    <TD>ramb18_fixed=0</TD>
    <TD>ramb18_used=1</TD>
    <TD>ramb18_util_percentage=0.83</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb18e1_only_used=1</TD>
    <TD>ramb36_fifo_available=60</TD>
    <TD>ramb36_fifo_fixed=0</TD>
    <TD>ramb36_fifo_used=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb36_fifo_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>primitives</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bufg_functional_category=Clock</TD>
    <TD>bufg_used=4</TD>
    <TD>carry4_functional_category=CarryLogic</TD>
    <TD>carry4_used=32</TD>
</TR><TR ALIGN='LEFT'>    <TD>fdce_functional_category=Flop &amp; Latch</TD>
    <TD>fdce_used=112</TD>
    <TD>fdpe_functional_category=Flop &amp; Latch</TD>
    <TD>fdpe_used=6</TD>
</TR><TR ALIGN='LEFT'>    <TD>fdre_functional_category=Flop &amp; Latch</TD>
    <TD>fdre_used=74</TD>
    <TD>fdse_functional_category=Flop &amp; Latch</TD>
    <TD>fdse_used=4</TD>
</TR><TR ALIGN='LEFT'>    <TD>ibuf_functional_category=IO</TD>
    <TD>ibuf_used=2</TD>
    <TD>lut1_functional_category=LUT</TD>
    <TD>lut1_used=10</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut2_functional_category=LUT</TD>
    <TD>lut2_used=44</TD>
    <TD>lut3_functional_category=LUT</TD>
    <TD>lut3_used=10</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut4_functional_category=LUT</TD>
    <TD>lut4_used=45</TD>
    <TD>lut5_functional_category=LUT</TD>
    <TD>lut5_used=43</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut6_functional_category=LUT</TD>
    <TD>lut6_used=26</TD>
    <TD>mmcme2_adv_functional_category=Clock</TD>
    <TD>mmcme2_adv_used=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>obuf_functional_category=IO</TD>
    <TD>obuf_used=1</TD>
    <TD>ramb18e1_functional_category=Block Memory</TD>
    <TD>ramb18e1_used=1</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>slice_logic</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>f7_muxes_available=8800</TD>
    <TD>f7_muxes_fixed=0</TD>
    <TD>f7_muxes_used=0</TD>
    <TD>f7_muxes_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>f8_muxes_available=4400</TD>
    <TD>f8_muxes_fixed=0</TD>
    <TD>f8_muxes_used=0</TD>
    <TD>f8_muxes_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_logic_available=17600</TD>
    <TD>lut_as_logic_fixed=0</TD>
    <TD>lut_as_logic_used=143</TD>
    <TD>lut_as_logic_util_percentage=0.81</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_memory_available=6000</TD>
    <TD>lut_as_memory_fixed=0</TD>
    <TD>lut_as_memory_used=0</TD>
    <TD>lut_as_memory_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>register_as_flip_flop_available=35200</TD>
    <TD>register_as_flip_flop_fixed=0</TD>
    <TD>register_as_flip_flop_used=196</TD>
    <TD>register_as_flip_flop_util_percentage=0.56</TD>
</TR><TR ALIGN='LEFT'>    <TD>register_as_latch_available=35200</TD>
    <TD>register_as_latch_fixed=0</TD>
    <TD>register_as_latch_used=0</TD>
    <TD>register_as_latch_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_luts_available=17600</TD>
    <TD>slice_luts_fixed=0</TD>
    <TD>slice_luts_used=143</TD>
    <TD>slice_luts_util_percentage=0.81</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_registers_available=35200</TD>
    <TD>slice_registers_fixed=0</TD>
    <TD>slice_registers_used=196</TD>
    <TD>slice_registers_util_percentage=0.56</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_distributed_ram_fixed=0</TD>
    <TD>lut_as_distributed_ram_used=0</TD>
    <TD>lut_as_logic_available=17600</TD>
    <TD>lut_as_logic_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_logic_used=143</TD>
    <TD>lut_as_logic_util_percentage=0.81</TD>
    <TD>lut_as_memory_available=6000</TD>
    <TD>lut_as_memory_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_memory_used=0</TD>
    <TD>lut_as_memory_util_percentage=0.00</TD>
    <TD>lut_as_shift_register_fixed=0</TD>
    <TD>lut_as_shift_register_used=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_in_front_of_the_register_is_unused_fixed=0</TD>
    <TD>lut_in_front_of_the_register_is_unused_used=35</TD>
    <TD>lut_in_front_of_the_register_is_used_fixed=35</TD>
    <TD>lut_in_front_of_the_register_is_used_used=18</TD>
</TR><TR ALIGN='LEFT'>    <TD>register_driven_from_outside_the_slice_fixed=18</TD>
    <TD>register_driven_from_outside_the_slice_used=53</TD>
    <TD>register_driven_from_within_the_slice_fixed=53</TD>
    <TD>register_driven_from_within_the_slice_used=143</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_available=4400</TD>
    <TD>slice_fixed=0</TD>
    <TD>slice_registers_available=35200</TD>
    <TD>slice_registers_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_registers_used=196</TD>
    <TD>slice_registers_util_percentage=0.56</TD>
    <TD>slice_used=82</TD>
    <TD>slice_util_percentage=1.86</TD>
</TR><TR ALIGN='LEFT'>    <TD>slicel_fixed=0</TD>
    <TD>slicel_used=53</TD>
    <TD>slicem_fixed=0</TD>
    <TD>slicem_used=29</TD>
</TR><TR ALIGN='LEFT'>    <TD>unique_control_sets_available=4400</TD>
    <TD>unique_control_sets_fixed=4400</TD>
    <TD>unique_control_sets_used=14</TD>
    <TD>unique_control_sets_util_percentage=0.32</TD>
</TR><TR ALIGN='LEFT'>    <TD>using_o5_and_o6_fixed=0.32</TD>
    <TD>using_o5_and_o6_used=35</TD>
    <TD>using_o5_output_only_fixed=35</TD>
    <TD>using_o5_output_only_used=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>using_o6_output_only_fixed=0</TD>
    <TD>using_o6_output_only_used=108</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>specific_feature</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bscane2_available=4</TD>
    <TD>bscane2_fixed=0</TD>
    <TD>bscane2_used=0</TD>
    <TD>bscane2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>capturee2_available=1</TD>
    <TD>capturee2_fixed=0</TD>
    <TD>capturee2_used=0</TD>
    <TD>capturee2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>dna_port_available=1</TD>
    <TD>dna_port_fixed=0</TD>
    <TD>dna_port_used=0</TD>
    <TD>dna_port_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>efuse_usr_available=1</TD>
    <TD>efuse_usr_fixed=0</TD>
    <TD>efuse_usr_used=0</TD>
    <TD>efuse_usr_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>frame_ecce2_available=1</TD>
    <TD>frame_ecce2_fixed=0</TD>
    <TD>frame_ecce2_used=0</TD>
    <TD>frame_ecce2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>icape2_available=2</TD>
    <TD>icape2_fixed=0</TD>
    <TD>icape2_used=0</TD>
    <TD>icape2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>startupe2_available=1</TD>
    <TD>startupe2_fixed=0</TD>
    <TD>startupe2_used=0</TD>
    <TD>startupe2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>xadc_available=1</TD>
    <TD>xadc_fixed=0</TD>
    <TD>xadc_used=0</TD>
    <TD>xadc_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>synthesis</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-assert=default::[not_specified]</TD>
    <TD>-bufg=default::12</TD>
    <TD>-cascade_dsp=default::auto</TD>
    <TD>-constrset=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-control_set_opt_threshold=default::auto</TD>
    <TD>-directive=default::default</TD>
    <TD>-fanout_limit=default::10000</TD>
    <TD>-flatten_hierarchy=default::rebuilt</TD>
</TR><TR ALIGN='LEFT'>    <TD>-fsm_extraction=default::auto</TD>
    <TD>-gated_clock_conversion=default::off</TD>
    <TD>-generic=default::[not_specified]</TD>
    <TD>-include_dirs=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-keep_equivalent_registers=default::[not_specified]</TD>
    <TD>-max_bram=default::-1</TD>
    <TD>-max_bram_cascade_height=default::-1</TD>
    <TD>-max_dsp=default::-1</TD>
</TR><TR ALIGN='LEFT'>    <TD>-max_uram=default::-1</TD>
    <TD>-max_uram_cascade_height=default::-1</TD>
    <TD>-mode=default::default</TD>
    <TD>-name=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-no_lc=default::[not_specified]</TD>
    <TD>-no_srlextract=default::[not_specified]</TD>
    <TD>-no_timing_driven=default::[not_specified]</TD>
    <TD>-part=xc7z010clg400-2</TD>
</TR><TR ALIGN='LEFT'>    <TD>-resource_sharing=default::auto</TD>
    <TD>-retiming=default::[not_specified]</TD>
    <TD>-rtl=default::[not_specified]</TD>
    <TD>-rtl_skip_constraints=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-rtl_skip_ip=default::[not_specified]</TD>
    <TD>-seu_protect=default::none</TD>
    <TD>-sfcu=default::[not_specified]</TD>
    <TD>-shreg_min_size=default::3</TD>
</TR><TR ALIGN='LEFT'>    <TD>-top=uart_top</TD>
    <TD>-verilog_define=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>elapsed=00:00:18s</TD>
    <TD>hls_ip=0</TD>
    <TD>memory_gain=617.938MB</TD>
    <TD>memory_peak=1010.016MB</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>xsim</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-sim_mode=behavioral</TD>
    <TD>-sim_type=default::</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
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